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MC14516B Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is constructed with MOS P-channel and N-channel enhancement mode devices in a monolithic structure. This counter can be preset by applying the desired value, in binary, to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset Enable (PE) high. The direction of counting is controlled by applying a high (for up counting) or a low (for down counting) to the UP/DOWN input. The state of the counter changes on the positive transition of the clock input. Cascading can be accomplished by connecting the Carry Out to the Carry In of the next stage while clocking each counter in parallel. The outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high to the reset (R) pin. This CMOS counter finds primary use in up/down and difference counting. Other applications include: (1) Frequency synthesizer applications where low power dissipation and/or high noise immunity is desired, (2) Analog-to-digital and digital-to-analog conversions, and (3) Magnitude and sign generation.
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16 PDIP-16 P SUFFIX CASE 648 MC14516BCP AWLYYWW 1 16 SOIC-16 D SUFFIX CASE 751B 1 16 SOEIAJ-16 F SUFFIX CASE 966 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week MC14516B ALYW 14516B AWLYWW
* * * * * * *
Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Internally Synchronous for High Speed Logic Edge-Clocked Design -- Count Occurs on Positive Going Edge of Clock Single Pin Reset Asynchronous Preset Enable Operation Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky Load Over the Rated Temperature Range
ORDERING INFORMATION MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V MC14516BD V MC14516BDR2 mA mW C C C MC14516BF MC14516BFEL SOIC-16 SOEIAJ-16 SOEIAJ-16 2500/Tape & Reel See Note 1. See Note 1. SOIC-16 48/Rail Device MC14516BCP Package PDIP-16 Shipping 2000/Box
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C
(c) Semiconductor Components Industries, LLC, 2000
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August, 2000 - Rev. 4
Publication Order Number: MC14516B/D
MC14516B
PIN ASSIGNMENT
PE Q3 P3 P0 CARRY IN Q0 CARRY OUT VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD C Q2 P2 P1 Q1 U/D R
BLOCK DIAGRAM
1 5 9 10 15 4 12 13 3 PE CARRY IN RESET UP/DOWN CLOCK P0 P1 P2 P3 CARRY OUT VDD = PIN 16 VSS = PIN 8 7 Q3 2 Q2 14 Q1 11 Q0 6
TRUTH TABLE
Carry In 1 0 0 X X Up/Down X 1 0 X X Preset Enable 0 0 0 1 X Reset 0 0 0 0 1 X X Clock X Action No Count Count Up Count Down Preset Reset
X = Don't Care NOTE: When counting up, the Carry Out signal is normally high and is low only when Q0 through Q3 are high and Carry In is low. When counting down, Carry Out is low only when Q0 through Q3 and Carry In are low.
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MC14516B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ (4.) 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc IT IT = (0.58 A/kHz) f + IDD IT = (1.20 A/kHz) f + IDD IT = (1.70 A/kHz) f + IDD Adc 4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001.
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MC14516B
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SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Characteristic All Types Typ (8.) 100 50 40 Symbol tTLH, tTHL VDD 5.0 10 15 Min -- -- -- Max 200 100 80 Unit ns Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time Clock to Q tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns Clock to Carry Out tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns Carry In to Carry Out tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = ( (0.5 ns/pF) CL + 75 ns ) Preset or Reset to Q tPLH, tPHL = (1.7 ns/pF) CL + 230 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = ( (0.5 ns/pF) CL + 75 ns ) Preset or Reset to Carry Out tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPLH, tPHL = (0.66 ns/pF) CL + 192 ns tPLH, tPHL = (0.5 ns/pF) CL + 125 ns Reset Pulse Width tPLH, tPHL 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 380 200 160 350 170 140 -- -- -- 315 130 100 315 130 100 180 80 60 315 130 100 550 225 150 190 100 80 200 100 75 3.0 6.0 8.0 630 260 200 ns 630 260 200 ns 360 160 120 ns 630 360 200 ns 1100 450 300 -- -- -- -- -- -- 1.5 3.0 4.0 ns ns tPLH, tPHL tPLH, tPHL tPLH, tPHL tw Clock Pulse Width tWH ns Clock Pulse Frequency fcl MHz 7. The formulas given are for the typical characteristics only at 25_C. 8. Data labelled "Typ" is not to be used for design purposes but is intended as an Indication of the IC's potential performance.
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MC14516B
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SWITCHING CHARACTERISTICS (9.) (CL = 50 pF, TA = 25_C) (continued)
Characteristic Symbol trem All Types Typ (10.) 325 115 90 -- -- -- 130 60 50 - 60 - 20 0 250 100 75 - 160 - 60 - 40 - 120 - 70 - 50 240 210 210 100 50 40 VDD 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min 650 230 180 -- -- -- 260 120 100 0 20 20 500 200 150 - 70 - 10 0 - 40 - 30 - 25 480 420 420 200 100 80 Max -- -- 15 5 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- s Unit ns Preset or Reset Removal Time The Preset or Reset signal must be low prior to a positive-going transition of the clock. Clock Rise and Fall Time tTLH, tTHL tsu Setup Time Carry In to Clock Hold Time Clock to Carry In Setup Time Up/Down to Clock Hold Time Clock to Up/Down Setup Time Pn to PE Hold Time PE to Pn Preset Enable Pulse Width ns th ns tsu ns th ns tsu ns th ns tWH ns 9. The formulas given are for the typical characteristics only at 25_C. 10. Data labelled "Typ" is not to be used for design purposes but is intended as an Indication of the IC's potential performance.
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MC14516B
VDD 500 pF ID 0.01 F CERAMIC
PE
Q0 20 ns CL CL CL CL CL CLOCK 50% 90% VARIABLE WIDTH 10% 20 ns VDD VSS
PULSE GENERATOR
CARRY IN R Q1 UP/DOWN CLOCK P0 P1 P2 P3 Q2 Q3 CARRY OUT
Figure 1. Power Dissipation Test Circuit and Waveform LOGIC DIAGRAM
P0 4 RESET 9 Q0 6 P1 Q1 12 11 P2 13 Q2 14 P3 3 Q3 2
PRESET ENABLE
1 P P P P
CLOCK 15 PE CARRY OUT 7 C T
Q
PE C
Q
PE C
Q
PE C
Q
Q
T
Q
T
Q
T
Q
CARRY IN
5
UP/DOWN 10
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MC14516B
TOGGLE FLIP-FLOP
PARALLEL IN PE C T Q P Q
FLIP-FLOP FUNCTIONAL TRUTH TABLE
Preset Enable 1 0 0 0 X = Don't Care Clock X T X 0 1 X Qn+1 Parallel In Qn Qn Qn
tsu CARRY IN OR UP/DOWN th 50% 50% tw(H) tw(H)
trem
1 fcl
VDD VSS VDD VSS VDD tTLH 90% 10% VSS VOH VOL
CLOCK PRESET ENABLE Q0 OR CARRY OUT
CARRY OUT ONLY 90% 10% tPHL trem
50%
tTHL
tPLH
tPLH VDD VSS
RESET tw
Figure 2. Switching Time Waveforms
PIN DESCRIPTIONS
INPUTS CONTROLS
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) -- Data on these inputs is loaded into the counter when PE is taken high. Carry In, (Pin 5) -- This active-low input is used when Cascading stages. Carry In is usually connected to Carry Out of the previous stage. While high, Clock is inhibited. Clock, (Pin 15) -- Binary data is incremented or decremented, depending on the direction of count, on the positive transition of this input.
OUTPUTS
PE, Preset Enable, (Pin 1) -- Asynchronously loads data on the Preset Inputs. This pin is active high and inhibits the clock when high. R, Reset, (Pin 9) -- Asynchronously resets the Q out- puts to a low state. This pin is active high and inhibits the clock when high. Up/Down, (Pin 10) -- Controls the direction of count, high for up count, low for down count.
SUPPLY PINS
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) -- Binary data is present on these outputs with Q0 corresponding to the least significant bit. Carry Out, (Pin 7) -- Used when cascading stages, Carry Out is usually connected to Carry In of the next stage. This synchronous output is active low and may also be used to indicate terminal count.
VSS, Negative Supply Voltage, (Pin 8) -- This pin is usually connected to ground. VDD, Positive Supply Voltage, (Pin 16) -- This pin is connected to a positive supply voltage ranging from 3.0 volts to 18.0 volts.
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MC14516B
Q0 PRESET ENABLE 0 = COUNT 1 = PRESET 1 = UP 0 = DOWN Q0 PE Cin CLOCK U/D R P0 Q1 Q2 Q3 Cout Q0 PE Cin CLOCK U/D R P0 Q1 Q2 Q3 Cout TERMINAL COUNT INDICATOR Q1 Q2 Q3 Q4 Q5 Q6 Q7
L.S.D. MC14516B P1 P2
M.S.D. MC14516B P1 P2
P3
P3
P0
P1
P2
P3
P4
P5
P6
P7
+VDD CLOCK +VDD RESET OPEN = COUNT THUMBWHEEL SWITCHES (OPEN FOR 0")
+VDD RESISTORS = 10 kW
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant Digit (M.S.D.) is disabled while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count. (See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
Figure 3. Presettable Cascaded 8-Bit Up/Down Counter
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CLOCK UP/DOWN
TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8-BIT UP/DOWN COUNTER
CARRY IN (MSD) PE P7 P6 P5 P4 P3 P2 P1
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P0 CARRY OUT (MSD) Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 CARRY OUT (LSD) RESET COUNT 13 14 15 16 17 18 19 18 17 16 15 14 13 251 PRESET ENABLE DOWN COUNT UP COUNT 252 253 254 255 0 1 2 3 2 1 0 1 2
MC14516B
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PRESET ENABLE UP COUNT
RESET DOWN COUNT UP COUNT
MC14516B
fout Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 BUFFER
Q0 PE Cin CLOCK U/D R P0
Q1
Q2
Q3 Cout
Q0 PE Cin CLOCK U/D R P0
Q1
Q2
Q3 Cout
L.S.D. MC14516B P1 P2
M.S.D. MC14516B P1 P2
P3
P3
P0
P1
P2
P3
P4
P5
P6
P7
+VDD CLOCK (fin) +VDD RESET OPEN = COUNT THUMBWHEEL SWITCHES (OPEN FOR 0")
+VDD RESISTORS = 10 kW fout = fin n
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example, the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation, both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
Figure 4. Programmable Cascaded Frequency Divider
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MC14516B
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
-A-
16 9
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC14516B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
LE Q1 E HE
1 8
16
9
M_ L DETAIL P
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14516B/D

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